Evolution of Digital Signal Processors

Introduction

Digital Signal Processing deals with algorithms for handling large chunk of data. This branch identified itself as a separate subject in 70s when engineers thought about processing the signals arising from nature in the discrete form. Development of Sampling Theory followed and the design of Analog-to-Digital converters gave an impetus in this direction. The contemporary applications of digital signal processing was mainly in speech followed by Communication, Seismology, Biomedical etc. Later on the field of Image processing emerged as another important area in signal processing.

The following broadly defines different processor classes

• General Purpose - high performance

- Pentiums, Alpha's, SPARC
- Used for general purpose software
- Heavy weight OS - UNIX, NT
- Workstations, PC's

• Embedded processors and processor cores

- ARM, 486SX, Hitachi SH7000, NEC V800
- Single program
- Lightweight, real-time OS
- DSP support
- Cellular phones, consumer electronics (e. g. CD players)

• Microcontrollers

- Extremely cost sensitive
- Small word size - 8 bit common
- Highest volume processors by far
- Automobiles, toasters, thermostats, ...

A Digital Signal Processor is required to do the following Digital Signal Processing tasks in real time.

• Signal Modeling

- Difference Equation
- Convolution
- Transfer Function
- Frequency Response

• Signal Processing

- Data Manipulation
- Algorithms
- Filtering
- Estimation


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Question and Answere

Q1. Discuss different types of cache mappings.

Ans:
Direct, Fully Associative, Set Associative.

Q2. Discuss the size of the cache memory on the system performance.

Ans:



Q3. Discuss the differences between EDORAM and SDRAM

Ans:
EDO RAM



SDRAM



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DRAM Integration Problem and Memory Management Unit (MMU)

DRAM Integration Problem

• SRAM easily integrated on same chip as processor.

• DRAM more difficult.
o Different chip making process between DRAM and conventional logic.
o Goal of conventional logic (IC) designers:
- minimize parasitic capacitance to reduce signal propagation delays and power consumption.
o Goal of DRAM designers:
- create capacitor cells to retain stored information.
o Integration processes beginning to appear.

Memory Management Unit (MMU)

• Duties of MMU
- Handles DRAM refresh, bus interface and arbitration.
- Takes care of memory sharing among multiple processors.
- Translates logic memory addresses from processor to physical memory addresses of DRAM.

• Modern CPUs often come with MMU built-in.

• Single-purpose processors can be used.

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Variations of DRAMs

Fast Page Mode DRAM (FPM DRAM)

• Each row of memory bit array is viewed as a page.
• Page contains multiple words.
• Individual words addressed by column address.
• Timing diagram:
- row (page) address sent.
- 3 words read consecutively by sending column address for each
extra cycle eliminated on each read/write of words from same.



Extended data out DRAM (EDO DRAM)

• Improvement of FPM DRAM.
• Extra latch before output buffer.
- allows strobing of cas before data read operation completed.
• Reduces read/write latency by additional cycle.



(S)ynchronous and Enhanced Synchronous (ES) DRAM

• SDRAM latches data on active edge of clock.
• Eliminates time to detect ras/cas and rd/wr signals.
• A counter is initialized to column address then incremented on active edge of clock to access consecutive memory locations.
• ESDRAM improves SDRAM
- added buffers enable overlapping of column addressing.
- faster clocking and lower read/write latency possible.



Rambus DRAM (RDRAM)

• More of a bus interface architecture than DRAM architecture.
• Data is latched on both rising and falling edge of clock.
• Broken into 4 banks each with own row decoder.
- can have 4 pages open at a time.
• Capable of very high throughput.


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Advanced RAM

Intoducation

• DRAMs commonly used as main memory in processor based embedded systems.
- high capacity, low cost.

• Many variations of DRAMs proposed.
- need to keep pace with processor speeds.
- FPM DRAM: fast page mode DRAM.
- EDO DRAM: extended data out DRAM.
- SDRAM/ESDRAM: synchronous and enhanced synchronous DRAM.
- RDRAM: rambus DRAM.

Basic DRAM

• Address bus multiplexed between row and column components.
• Row and column addresses are latched in, sequentially, by strobing ras (row address strobe) and cas (column address strobe) signals, respectively.
• Refresh circuitry can be external or internal to DRAM device.
- strobes consecutive memory address periodically causing memory content to be refreshed.
- Refresh circuitry disabled during read or write operation.



Note: In computer or memory technology, a strobe is a signal that is sent that validates data or other signals on adjacent parallel lines. In memory technology, the CAS (column address strobe) and RAS ( row address strobe ) signals are used to tell a dynamic RAM that an address is a column or row address.

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Techniques and Performance of Cache

Cache-Replacement Policy

• Technique for choosing which block to replace.
- when fully associative cache is full.
- when set-associative cache’s line is full.

• Direct mapped cache has no choice.

• Random.
- replace block chosen at random.

• LRU: least-recently used
- replace block not accessed for longest time.

• FIFO: first-in-first-out
- push block onto queue when accessed.
- choose block to replace by popping queue.

Cache Write Techniques

• When written, data cache must update main memory.

• Write-through
- write to main memory whenever cache is written to
easiest to implement.
- processor must wait for slower main memory write
potential for unnecessary writes.

• Write-back
- main memory only written when “dirty” block replaced.
- extra dirty bit for each block set when cache block written to
reduces number of slow main memory writes.

Cache Impact on System Performance

• Most important parameters in terms of performance:

• Total size of cache
- total number of data bytes cache can hold.
- tag, valid and other house keeping bits not included in total

• Degree of associativity.

• Data block size.

• Larger caches achieve lower miss rates but higher access cost.

• Example:
- 2 Kbyte cache: miss rate = 15%, hit cost = 2 cycles, miss cost = 20 cycles
- avg. cost of memory access
= (0.85 * 2) + (0.15 * 20) = 4.7 cycles

• 4 Kbyte cache: miss rate = 6.5%, hit cost = 3 cycles, miss cost will not change.
- avg. cost of memory access = (0.935 * 3) + (0.065 * 20) = 4.105 cycles (improvement).

• 8 Kbyte cache: miss rate = 5.565%, hit cost = 4 cycles, miss cost will not change.
- avg. cost of memory access = (0.94435 * 4) + (0.05565 * 20) = 4.8904 cycles.

Cache Performance Trade-Offs

• Improving cache hit rate without increasing size
- Increase line size
- Change set-associativity



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Basic Techniques of Cache Mapping

Direct Mapping

• Main memory address divided into 2 fields:

•Index which contains
- cache address.
- number of bits determined by cache size.
•Tag
- compared with tag stored in cache at address indicated by index.
- if tags match, check valid bit.

• Valid bit
-indicates whether data in slot has been loaded from memory.

• Offset
-used to find particular word in cache line.



Fully Associative Mapping

• Complete main memory address stored in each cache address.
• All addresses stored in cache simultaneously compared with desired address.
• Valid bit and offset same as direct mapping.



Set-Associative Mapping

• Compromise between direct mapping and fully associative mapping.
• Index same as in direct mapping.
• But, each cache address contains content and tags of 2 or more memory address locations.
• Tags of that set simultaneously compared as in fully associative mapping.
• Cache with set size N called N-way set-associative.
- 2-way, 4-way, 8-way are common.




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