FIR filter

General Purpose Processor

loop:

lw x0, (r0)
lw y0, (r1)
mul a, x0,y0
add b,a,b
inc r0
inc r1
dec ctr
tst ctr
jnz loop
sw b,(r2)
inc r2

This program assumes that the finite window of input signal is stored at the memory location starting from the address specified by r1 and the equal number filter coefficients are stored at the memory location starting from the address specified by r0. The result will be stored at the memory location starting from the address specified by r2. The program assumes the content of the register b as 0 before the start of the loop.

lw x0, (r0)
lw y0, (r1)

These two instructions load x0 and y0 registers with values from the memory location specified by the registers r0 and r1 with values x0 and y0.

mul a, x0,y0
This instruction multiplies x0 with y0 and stores the result in a.

add b,a,b
This instruction adds a with b (which contains already accumulated result from the previous operation) and stores the result in b.

inc r0
inc r1
dec ctr
tst ctr
jnz loop

The above portion of the program increment the registers to point to the next memory location, decrement the counters, to see if the filter order has been reached and tests for 0. It jumps to the start of the loop.

sw b,(r2)
inc r2

This stores the final result and increments the register r2 to point to the next location.

Let us see the program for an early DSP TMS32010 developed by Texas

Instruments in 80s.
It has got the following features
• 16-bit fixed-point
• Harvard architecture separate instruction and data memories
• Accumulator
• Specialized instruction set Load and Accumulate
• 390 ns Multiple-Accumulate(MAC)

TI TMS32010 (Ist DSP) 1982



The program for the FIR filter (for a 3rd order) is given as follows:

Here X4, H4, ... are direct (absolute) memory addresses:
LT X4 ;Load T with x(n-4)
MPY H4 ;P = H4*X4
;Acc = Acc + P
LTD X3 ;Load T with x(n-3); x(n-4) = x(n-3);
MPY H3 ; P = H3*X3
; Acc = Acc + P
LTD X2
MPY H2
...

• Two instructions per tap, but requires unrolling.
; for comment lines.
LT X4 Loading from direct address X4.
MPY H4 Multiply and accumulate.
LTD X3 Loading and shifting in the data points in the memory.

The advantages of the DSP over the General Purpose Processor can be written as Multiplication and Accumulation takes place at a time. Therefore this architecture supports filtering kind of tasks. The loading and subsequent shifting is also takes place at a time.

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