Debug a microcontroller-to-FPGA interface from the FPGA side

Microcontrollers and FPGAs often work together in embedded systems. As more functions move into the FPGA, however, debugging the interface between the two devices becomes more difficult. The traditional debugging approach comes from the microcontroller side, which relies on a serial-port printout. This approach adds overhead and may cause timing problems. Furthermore, this approach cannot guarantee uninterrupted and exclusive access to certain addresses because of operating-system multitasking. Thus, a serial-port printout doesn’t accurately describe the actions on the microcontroller/FPGA interface.

Instead, you can approach the problem from the FPGA side using a JTAG (Joint Test Action Group) interface as a communication port. This approach uses the internal logic of the FPGA to capture the read/write transactions on the microcontroller/FPGA interface. This method is nonintrusive because the circuit that captures transactions sits between the microcontroller and the FPGA’s functioning logic and monitors the data without interfering with it. It stores the captured transaction in the FPGA’s RAM resources in real time. You can transfer the data to a PC through the JTAG port’s download cable.

The debugging tool comprises the data-capture circuit, the JTAG communication circuit, and the GUI (graphical user interface). The data-capture circuit uses standard HDL (hardware-description language) and instantiates a FIFO (first-in/first-out) buffer in the FPGA. Whenever you read or write to a register, the debugging tool records the corresponding value of the address and data on the bus and stores it in the FIFO buffer. You can retrieve the data through the JTAG’s download cable to the PC (Listing 1 - all listings are provided on subsequent pages or as a downloadable doc file from the links below).

Because the FPGA has limited on-chip RAM resources, you must keep the FIFO buffer shallow. To efficiently use the FIFO buffer, the design includes filter and trigger circuits. With inclusive address filtering, the circuit monitors only several discontinuous spans of addresses instead of the whole address space. Exclusive-address filters can filter out several smaller address spans from the inclusive-address spans, enabling finer control of the filter settings (Listing 2).

With transaction triggering, the circuit starts when you read from or write to a certain address. You can add certain data values to the triggering condition (Listing 3). You can dynamically reconfigure the settings of address filters and transaction triggers through the JTAG’s vendor-supplied, customizable communication circuit without recompilation of the FPGA design (Figure 1). The circuit has two interfaces, one of which is written in HDL to form a customized JTAG chain. It communicates with the user logic (listing 1, listing 2, and listing 3). The circuit is accessible through specific programming interfaces on the PC and communicates with the user program or GUI (Listing 4).



The FPGA-based circuit facilitates writing and reading functions from PC to FPGA logic, and it promotes the JTAG interface to a general communication port attached to the FPGA. FPGA manufacturers, including Actel, Altera, Lattice Semiconductor, and Xilinx, respectively, call this circuit UJTAG (user JTAG), Virtual JTAG, ORCAstra, and BScan (references 1 through 4).

The GUI for this circuit uses Tcl/Tk (tool-command-language tool kit). FPGA manufacturers provide vendor-specific APIs (application-programming interfaces) in Tcl for the PC side of the JTAG-communication circuit. The APIs include basic functions, such as JTAG-chain initialization, selection, and data reading and writing. With the data-read function, you can check the capturing status and get the transaction data from the FIFO buffer. With the data-writing function, you can send the filter and trigger configuration data to the capturing circuit in the FPGA (Listing 4). The JTAG-based debugging method provides dynamic visibility and controllability into the microcontroller-to-FPGA interface and the FPGA’s internal logic without the need to recompile and download FPGA code.

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