Ans:
Microcontrollers usually have on chip RAM and ROM (or EPROM) in addition to on chip i/o hardware to minimize chip count in single chip solutions. As a result of using on chip hardware for I/O and RAM and ROM they usually have pretty low performance CPU. Microcontrollers also often have timers that generate interrupts and can thus be used with the CPU and on chip A/D D/A or parallel ports to get regularly timed I/O. The prime use of a microcontroller is to control the operations of a machine using a fixed program that is stored in ROM and does not change over the lifetime of the system. The microcontroller is concerned with getting data from and to its own pins; the architecture and instruction set are optimized to handle data in bit and byte size.
Digital Signal Processors have been designed based on the modified Harvard Architecture to handle real time signals. The features of these processors are suitable for implementing signal processing algorithms. One of the common operations required in such applications is array multiplication. For example convolution and correlation require array multiplication. This is accomplished by multiplication followed by accumulation and addition. This is generally carried out by Multiplier and Accumulator (MAC) units. Some times it is known as MACD, where D stands for Data move. Generally all the instructions are executed in single cycle. These DSP units generally use Multiple Access and Multi Ported Memory units. Multiple access memory allows more than one access in one clock period. The Multi-ported Memory allows multiple addresses as well Data ports. This also increases the number of access per unit clock cycle.
Q2. Name few chips in each of the family of processors such as: Microcontroller, Digital Signal Processor, General Purpose Processor
Ans:
Microcontroller: Intel 8051, Intel 80196, Motorola 68705
Digital Signal Processors: TI 3206711, TI 3205000
General Purpose Processor: Intel Pentium IV, Power PC
Q3. Enlist the following in the increasing order of their access speed
Flash Memory, Dynamic Memory, Cache Memory, CDROM, Hard Disk, Magnetic Tape, Processor Memory
Ans:
Magnetic Tape, CDROM, Hard Disk, Dynamic Memory, Flash Memory, Cache Memory, Processor Memory
Q4. Draw the circuit of an anti-aliasing Filter using Operational amplifiers
Ans:
Q5. Is it possible to implement an anti-aliasing filter in the digital form?
Ans:
No it is not possible to implement an anti-aliasing filter in digital form. Because aliasing is an error introduced at the sampling phase of analog to digital converter. If the sampling frequency is less than twice of the highest frequency present the higher signal frequencies fold back to lower frequency band and hence can be distinguished in the digital/discrete domain.
Q6. State with justification if the following statements are right (or wrong)
Cache memory can be a static RAM
Dynamic RAMs occupy more space per word storage
The full-form of SDRAM is static-dynamic RAM
BIOS in your PC is not a Random Access Memory (RAM)
Ans:
Cache memory can be a static RAM right
The cache memory need to have very fast access time which is possible with static RAM.
Dynamic RAMs occupy more space per word storage wrong
DRAMs are basically simple MOS based capacitors. Therefore occupy much lower space as compared to static RAMs.
The full-form of SDRAM is static-dynamic RAM wrong
SDRAM is Synchronous Dynamic RAM.
BIOS in your PC is not a Random Access Memory (RAM) Wrong
The BIOS is a CMOS based memory which can be accessed uniformly.
Q7. Explain the function of the following units in a general purpose processor
Instruction Register
Program Counter
Instruction Queue
Control Unit
Ans:
Instruction Register: A register inside the CPU which holds the instruction code temporarily before sending it to the decoding unit.
Program Counter: It is a register inside the CPU which holds the address of the next instruction code in a program. It gets updated automatically by the address generation unit.
Instruction Queue: A set of memory locations inside the CPU to hold the instructions in a pipe-line before rending them to the next instruction decoding unit.
Control Unit: This is responsible in generating timing and control signals for various operations inside the CPU. It is very closely associated with the instruction decoding unit.
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