Evolution of Digital Signal Processors

Introduction

Digital Signal Processing deals with algorithms for handling large chunk of data. This branch identified itself as a separate subject in 70s when engineers thought about processing the signals arising from nature in the discrete form. Development of Sampling Theory followed and the design of Analog-to-Digital converters gave an impetus in this direction. The contemporary applications of digital signal processing was mainly in speech followed by Communication, Seismology, Biomedical etc. Later on the field of Image processing emerged as another important area in signal processing.

The following broadly defines different processor classes

• General Purpose - high performance

- Pentiums, Alpha's, SPARC
- Used for general purpose software
- Heavy weight OS - UNIX, NT
- Workstations, PC's

• Embedded processors and processor cores

- ARM, 486SX, Hitachi SH7000, NEC V800
- Single program
- Lightweight, real-time OS
- DSP support
- Cellular phones, consumer electronics (e. g. CD players)

• Microcontrollers

- Extremely cost sensitive
- Small word size - 8 bit common
- Highest volume processors by far
- Automobiles, toasters, thermostats, ...

A Digital Signal Processor is required to do the following Digital Signal Processing tasks in real time.

• Signal Modeling

- Difference Equation
- Convolution
- Transfer Function
- Frequency Response

• Signal Processing

- Data Manipulation
- Algorithms
- Filtering
- Estimation


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Question and Answere

Q1. Discuss different types of cache mappings.

Ans:
Direct, Fully Associative, Set Associative.

Q2. Discuss the size of the cache memory on the system performance.

Ans:



Q3. Discuss the differences between EDORAM and SDRAM

Ans:
EDO RAM



SDRAM



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DRAM Integration Problem and Memory Management Unit (MMU)

DRAM Integration Problem

• SRAM easily integrated on same chip as processor.

• DRAM more difficult.
o Different chip making process between DRAM and conventional logic.
o Goal of conventional logic (IC) designers:
- minimize parasitic capacitance to reduce signal propagation delays and power consumption.
o Goal of DRAM designers:
- create capacitor cells to retain stored information.
o Integration processes beginning to appear.

Memory Management Unit (MMU)

• Duties of MMU
- Handles DRAM refresh, bus interface and arbitration.
- Takes care of memory sharing among multiple processors.
- Translates logic memory addresses from processor to physical memory addresses of DRAM.

• Modern CPUs often come with MMU built-in.

• Single-purpose processors can be used.

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Variations of DRAMs

Fast Page Mode DRAM (FPM DRAM)

• Each row of memory bit array is viewed as a page.
• Page contains multiple words.
• Individual words addressed by column address.
• Timing diagram:
- row (page) address sent.
- 3 words read consecutively by sending column address for each
extra cycle eliminated on each read/write of words from same.



Extended data out DRAM (EDO DRAM)

• Improvement of FPM DRAM.
• Extra latch before output buffer.
- allows strobing of cas before data read operation completed.
• Reduces read/write latency by additional cycle.



(S)ynchronous and Enhanced Synchronous (ES) DRAM

• SDRAM latches data on active edge of clock.
• Eliminates time to detect ras/cas and rd/wr signals.
• A counter is initialized to column address then incremented on active edge of clock to access consecutive memory locations.
• ESDRAM improves SDRAM
- added buffers enable overlapping of column addressing.
- faster clocking and lower read/write latency possible.



Rambus DRAM (RDRAM)

• More of a bus interface architecture than DRAM architecture.
• Data is latched on both rising and falling edge of clock.
• Broken into 4 banks each with own row decoder.
- can have 4 pages open at a time.
• Capable of very high throughput.


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Advanced RAM

Intoducation

• DRAMs commonly used as main memory in processor based embedded systems.
- high capacity, low cost.

• Many variations of DRAMs proposed.
- need to keep pace with processor speeds.
- FPM DRAM: fast page mode DRAM.
- EDO DRAM: extended data out DRAM.
- SDRAM/ESDRAM: synchronous and enhanced synchronous DRAM.
- RDRAM: rambus DRAM.

Basic DRAM

• Address bus multiplexed between row and column components.
• Row and column addresses are latched in, sequentially, by strobing ras (row address strobe) and cas (column address strobe) signals, respectively.
• Refresh circuitry can be external or internal to DRAM device.
- strobes consecutive memory address periodically causing memory content to be refreshed.
- Refresh circuitry disabled during read or write operation.



Note: In computer or memory technology, a strobe is a signal that is sent that validates data or other signals on adjacent parallel lines. In memory technology, the CAS (column address strobe) and RAS ( row address strobe ) signals are used to tell a dynamic RAM that an address is a column or row address.

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Techniques and Performance of Cache

Cache-Replacement Policy

• Technique for choosing which block to replace.
- when fully associative cache is full.
- when set-associative cache’s line is full.

• Direct mapped cache has no choice.

• Random.
- replace block chosen at random.

• LRU: least-recently used
- replace block not accessed for longest time.

• FIFO: first-in-first-out
- push block onto queue when accessed.
- choose block to replace by popping queue.

Cache Write Techniques

• When written, data cache must update main memory.

• Write-through
- write to main memory whenever cache is written to
easiest to implement.
- processor must wait for slower main memory write
potential for unnecessary writes.

• Write-back
- main memory only written when “dirty” block replaced.
- extra dirty bit for each block set when cache block written to
reduces number of slow main memory writes.

Cache Impact on System Performance

• Most important parameters in terms of performance:

• Total size of cache
- total number of data bytes cache can hold.
- tag, valid and other house keeping bits not included in total

• Degree of associativity.

• Data block size.

• Larger caches achieve lower miss rates but higher access cost.

• Example:
- 2 Kbyte cache: miss rate = 15%, hit cost = 2 cycles, miss cost = 20 cycles
- avg. cost of memory access
= (0.85 * 2) + (0.15 * 20) = 4.7 cycles

• 4 Kbyte cache: miss rate = 6.5%, hit cost = 3 cycles, miss cost will not change.
- avg. cost of memory access = (0.935 * 3) + (0.065 * 20) = 4.105 cycles (improvement).

• 8 Kbyte cache: miss rate = 5.565%, hit cost = 4 cycles, miss cost will not change.
- avg. cost of memory access = (0.94435 * 4) + (0.05565 * 20) = 4.8904 cycles.

Cache Performance Trade-Offs

• Improving cache hit rate without increasing size
- Increase line size
- Change set-associativity



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Basic Techniques of Cache Mapping

Direct Mapping

• Main memory address divided into 2 fields:

•Index which contains
- cache address.
- number of bits determined by cache size.
•Tag
- compared with tag stored in cache at address indicated by index.
- if tags match, check valid bit.

• Valid bit
-indicates whether data in slot has been loaded from memory.

• Offset
-used to find particular word in cache line.



Fully Associative Mapping

• Complete main memory address stored in each cache address.
• All addresses stored in cache simultaneously compared with desired address.
• Valid bit and offset same as direct mapping.



Set-Associative Mapping

• Compromise between direct mapping and fully associative mapping.
• Index same as in direct mapping.
• But, each cache address contains content and tags of 2 or more memory address locations.
• Tags of that set simultaneously compared as in fully associative mapping.
• Cache with set size N called N-way set-associative.
- 2-way, 4-way, 8-way are common.




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Cache Memory

• Usually designed with SRAM.

-faster but more expensive than DRAM.

• Usually on same chip as processor.

- space limited, so much smaller than off-chip main memory.
- faster access (1 cycle vs. several cycles for main memory).

• Cache operation

- Request for main memory access (read or write)
- First, check cache for copy

- cache hit
*copy is in cache, quick access.

-cache miss
*copy not in cache, read address and possibly its neighbors into cache.

• Several cache design choices.
- cache mapping, replacement policies, and write techniques.

Cache Mapping

• is necessary as there are far fewer number of available cache addresses than the memory.

• Are address’ contents in cache?

• Cache mapping used to assign main memory address to cache address and determine hit or miss.

• Three basic techniques:
•Direct mapping.
• Fully associative mapping.
•Set-associative mapping.

• Caches partitioned into indivisible blocks or lines of adjacent memory addresses.
- usually 4 or 8 addresses per line.

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Memory Hierarchy

Objective is to use inexpensive, fast memory

• Main memory
Large, inexpensive, slow memory stores entire program and data.

• Cache
Small, expensive, fast memory stores copy of likely accessed parts of larger memory
Can be multiple levels of cache.




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Questions and Answers

Q1. Discuss the various control signals in a typical RAM device (say HM626)

Ans:



/OE: output enable bar: the output is enables when it is low. It is same as the read bar line
/WE: write enable bar: the line has to made low while writing to this device
CS1: chip select 1 bar: this line has to be made low along with CS2 bar to enable this chip
Q2. Download the datasheet of TC55V2325FF chip and indicate the various signals.

Ans:






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Composing memory

• Memory size needed often differs from size of readily available memories.

• When available memory is larger, simply ignore unneeded high-order address bits and higher data lines

• When available memory is smaller, compose several smaller memories into one larger memory.
– Connect side-by-side to increase width of words.
– Connect top to bottom to increase number of words.

• added high-order address line selects smaller memory containing desired word using a decoder.
– Combine techniques to increase number and width of words.










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Example

HM6264 & 27C256 RAM/ROM devices

• Low-cost low-capacity memory devices.
• Commonly used in 8-bit microcontroller-based embedded systems.
• First two numeric digits indicate device type.
– RAM: 62
– ROM: 27
• Subsequent digits indicate capacity in kilobits.




TC55V2325FF-100 memory device

• 2-megabit synchronous pipelined burst SRAM memory device.
• Designed to be interfaced with 32-bit processors.
• Capable of fast sequential reads and writes as well as single byte I/O.




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Flash Memory and RAM: “Random-access” memory

Flash Memory

It is an extension of EEPROM. It has the same floating gate principle and same write ability and storage permanence. It can be erased at a faster rate i.e. large blocks of memory erased at once, rather than one word at a time. The blocks are typically several thousand bytes large.

• Writes to single words may be slower.
– Entire block must be read, word updated, then entire block written back.
• Used with embedded systems storing large data items in nonvolatile memory.
– e.g., digital cameras, TV set-top boxes, cell phones.

RAM: “Random-access” memory




• Typically volatile memory
– bits are not held without power supply.

• Read and written to easily by embedded system during execution

• Internal structure more complex than ROM
– a word consists of several memory cells, each storing 1 bit
– each input and output data line connects to each cell in its column
– rd/wr connected to every cell
– when row is enabled by decoder, each cell has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read



Basic types of RAM

• SRAM: Static RAM
– Memory cell uses flip-flop to store bit.
– Requires 6 transistors.
– Holds data as long as power supplied.

• DRAM: Dynamic RAM
– Memory cell uses MOS transistor and capacitor to store bit.
– More compact than SRAM.
– “Refresh” required due to capacitor leak.

• word’s cells refreshed when read
– Typical refresh rate 15.625 microsec.
– Slower to access than SRAM.



Ram variations


• PSRAM: Pseudo-static RAM
– DRAM with built-in memory refresh controller.
– Popular low-cost high-density alternative to SRAM.

• NVRAM: Nonvolatile RAM
– Holds data after external power removed.
– Battery-backed RAM.

• SRAM with own permanently connected battery

• writes as fast as reads

• no limit on number of writes unlike nonvolatile ROM-based memory
– SRAM with EEPROM or flash stores complete RAM contents on EEPROM or flash before power.

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Common Memory Types

Read Only Memory (ROM)

This is a nonvolatile memory. It can only be read from but not written to, by a processor in an embedded system. Traditionally written to, “programmed”, before inserting to embedded system.

Uses
– Store software program for general-purpose processor.
• program instructions can be one or more ROM words.
– Store constant data needed by system.
– Implement combinational circuit.



Example

The figure shows the structure of a ROM. Horizontal lines represents the words. The vertical lines give out data. These lines are connected only at circles. If address input is 010 the decoder sets 2nd word line to 1. The data lines Q3 and Q1 are set to 1 because there is a “programmed” connection with word 2’s line. The word 2 is not connected with data lines Q2 and Q0. Thus the output is 1010.



Implementation of Combinatorial Functions

Any combinational circuit of n functions of same k variables can be done with 2k x n ROM. The inputs of the combinatorial circuit are the address of the ROM locations. The output is the word stored at that location.



Mask-programmed ROM

The connections “programmed” at fabrication. They are a set of masks. It can be written only once (in the factory). But it stores data for ever. Thus it has the highest storage permanence. The bits never change unless damaged. These are typically used for final design of high-volume systems.

OTP ROM: One-time programmable ROM

The Connections “programmed” after manufacture by user. The user provides file of desired contents of ROM. The file input to machine called ROM programmer. Each programmable connection is a fuse. The ROM programmer blows fuses where connections should not exist.
• Very low write ability: typically written only once and requires ROM programmer device.
• Very high storage permanence: bits don’t change unless reconnected to programmer and more fuses blown.
• Commonly used in final products: cheaper, harder to inadvertently modify.

EPROM: Erasable programmable ROM

This is known as erasable programmable read only memory. The programmable component is a MOS transistor. This transistor has a “floating” gate surrounded by an insulator. The Negative charges form a channel between source and drain storing a logic 1. The Large positive voltage at gate causes negative charges to move out of channel and get trapped in floating gate storing a logic 0. The (Erase) Shining UV rays on surface of floating-gate causes negative charges to return to channel from floating gate restoring the logic 1. An EPROM package showing quartz window through which UV light can pass.

The EPROM has:
• Better write ability
– can be erased and reprogrammed thousands of times
• Reduced storage permanence
– program lasts about 10 years but is susceptible to radiation and electric noise
• Typically used during design development



EEPROM

EEPROM is otherwise known as Electrically Erasable and Programmable Read Only Memory. It is erased typically by using higher than normal voltage. It can program and erase individual words unlike the EPROMs where exposure to the UV light erases everything.

The EEPROM has:
• Better write ability.
– can be in-system programmable with built-in circuit to provide higher than normal voltage.
• built-in memory controller commonly used to hide details from memory user.
– writes very slow due to erasing and programming.
• “busy” pin indicates to processor EEPROM still writing.
– can be erased and programmed tens of thousands of times.
• Similar storage permanence to EPROM (about 10 years).
• Far more convenient than EPROMs, but more expensive.

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Data Storage

An m word memory can store m x n: m words of n bits each. One word is located at one address therefore to address m words we need.

k = Log2(m) address input signals
or k number address lines can address m = 2k words

Example 4,096 x 8 memory:
• 32,768 bits
• 12 address input signals
• 8 input/output data signals



Memory access

The memory location can be accessed by placing the address on the address lines. The control lines read/write selects read or write. Some memory devices are multi-port i.e. multiple accesses to different locations simultaneously.



Memory Specifications

The specification of a typical memory is as follows:

The storage capacity: The number of bits/bytes or words it can store .

The memory access time (read access and write access): How long the memory takes to load the data on to its data lines after it has been addressed or how fast it can store the data upon supplied through its data lines. This reciprocal of the memory access time is known as Memory.

Bandwidth

The Power Consumption and Voltage Levels: The power consumption is a major factor in embedded systems. The lesser is the power consumption the more is packing density.
Size: Size is directly related to the power consumption and data storage capacity.





There are two important specifications for the Memory as far as Real Time Embedded Systems are concerned.
– Write Ability.
– Storage Performance.

Write ability

It is the manner and speed that a particular memory can be written.
• Ranges of write ability
– High end
• processor writes to memory simply and quickly e.g., RAM
– Middle range
• processor writes to memory, but slower e.g., FLASH, EEPROM (Electrically Erasable and Programmable Read Only Memory)
– Lower range
• special equipment, “programmer”, must be used to write to memory e.g., EPROM, OTP ROM (One Time Programmable Read Only Memory)
– Low end
• bits stored only during fabrication e.g., Mask-programmed ROM
• In-system programmable memory
– Can be written to by a processor in the embedded system using the memory
– Memories in high end and middle range of write ability

Storage permanence

It is the ability to hold the stored bits.

Range of storage permanence.
– High end
• essentially never loses bits.
• e.g., mask-programmed ROM.

– Middle range
• holds bits days, months, or years after memory’s power source turned off.
• e.g., NVRAM

– Lower range
• holds bits as long as power supplied to memory.
• e.g., SRAM

– Low end
• begins to lose bits almost immediately after written.
• e.g., DRAM

Nonvolatile memory
– Holds bits after power is no longer supplied.
– High end and middle range of storage permanence.


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The Memory Interface

Introducation

In a memory read operation the CPU loads the address onto the address bus. Most cases these lines are fed to a decoder which selects the proper memory location. The CPU then sends a read control signal. The data is stored in that location is transferred to the processor via the data lines.

In the memory write operation after the address is loaded the CPU sends the write control signal followed by the data to the requested memory location.

The memory can be classified in various ways i.e. based on the location, power consumption, way of data storage etc



The memory at the basic level can be classified as
1. Processor Memory (Register Array)
2. Internal on-chip Memory
3. Primary Memory
4. Cache Memory
5. Secondary Memory

Processor Memory (Register Array)

Most processors have some registers associated with the arithmetic logic units. They store the operands and the result of an instruction. The data transfer rates are much faster without needing any additional clock cycles. The number of registers varies from processor to processor. The more is the number the faster is the instruction execution. But the complexity of the architecture puts a limit on the amount of the processor memory.

Internal on-chip Memory

In some processors there may be a block of memory location. They are treated as the same way as the external memory. However it is very fast.

Primary Memory

This is the one which sits just out side the CPU. It can also stay in the same chip as of CPU. These memories can be static or dynamic.

Cache Memory

This is situated in between the processor and the primary memory. This serves as a buffer to the immediate instructions or data which the processor anticipates. There can be more than one levels of cache memory.

Secondary Memory

These are generally treated as Input/Output devices. They are much cheaper mass storage and slower devices connected through some input/output interface circuits. They are generally magnetic or optical memories such as Hard Disk and CDROM devices.
The memory can also be divided into Volatile and Non-volatile memory.

* Volatile Memory

The contents are erased when the power is switched off. Semiconductor Random Access Memories fall into this category.

* Non-volatile Memory

The contents are intact even of the power is switched off. Magnetic Memories (Hard Disks), Optical Disks (CDROMs), Read Only Memories (ROM) fall under this category.





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