Variations of DRAMs

Fast Page Mode DRAM (FPM DRAM)

• Each row of memory bit array is viewed as a page.
• Page contains multiple words.
• Individual words addressed by column address.
• Timing diagram:
- row (page) address sent.
- 3 words read consecutively by sending column address for each
extra cycle eliminated on each read/write of words from same.



Extended data out DRAM (EDO DRAM)

• Improvement of FPM DRAM.
• Extra latch before output buffer.
- allows strobing of cas before data read operation completed.
• Reduces read/write latency by additional cycle.



(S)ynchronous and Enhanced Synchronous (ES) DRAM

• SDRAM latches data on active edge of clock.
• Eliminates time to detect ras/cas and rd/wr signals.
• A counter is initialized to column address then incremented on active edge of clock to access consecutive memory locations.
• ESDRAM improves SDRAM
- added buffers enable overlapping of column addressing.
- faster clocking and lower read/write latency possible.



Rambus DRAM (RDRAM)

• More of a bus interface architecture than DRAM architecture.
• Data is latched on both rising and falling edge of clock.
• Broken into 4 banks each with own row decoder.
- can have 4 pages open at a time.
• Capable of very high throughput.


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