Cache Memory

• Usually designed with SRAM.

-faster but more expensive than DRAM.

• Usually on same chip as processor.

- space limited, so much smaller than off-chip main memory.
- faster access (1 cycle vs. several cycles for main memory).

• Cache operation

- Request for main memory access (read or write)
- First, check cache for copy

- cache hit
*copy is in cache, quick access.

-cache miss
*copy not in cache, read address and possibly its neighbors into cache.

• Several cache design choices.
- cache mapping, replacement policies, and write techniques.

Cache Mapping

• is necessary as there are far fewer number of available cache addresses than the memory.

• Are address’ contents in cache?

• Cache mapping used to assign main memory address to cache address and determine hit or miss.

• Three basic techniques:
•Direct mapping.
• Fully associative mapping.
•Set-associative mapping.

• Caches partitioned into indivisible blocks or lines of adjacent memory addresses.
- usually 4 or 8 addresses per line.

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