Digital Electronics

Introduction

The first single chip microprocessor came in 1971 by Intel Corporation. It was called Intel 4004 and that was the first single chip CPU ever built. We can say that was the first general purpose processor. Now the term microprocessor and processor are synonymous. The 4004 was a 4-bit processor, capable of addressing 1K data memory and 4K program memory. It was meant to be used for a simple calculator. The 4004 had 46 instructions, using only 2,300 transistors in a 16-pin DIP. It ran at a clock rate of 740kHz (eight clock cycles per CPU cycle of 10.8 microseconds). In 1975, Motorola introduced the 6800, a chip with 78 instructions and probably the first microprocessor with an index register. In 1979, Motorola introduced the 68000. With internal 32-bit registers and a 32-bit address space, its bus was still 16 bits due to hardware prices. On the other hand in 1976, Intel designed 8085 with more instructions to enable/disable three added interrupt pins (and the serial I/O pins).

They also simplified hardware so that it used only +5V power, and added clock-generator and bus-controller circuits on the chip. In 1978, Intel introduced the 8086, a 16-bit processor which gave rise to the x86 architecture. It did not contain floating-point instructions. In 1980 the company released the 8087, the first math co-processor they'd developed. Next came the 8088, the processor for the first IBM PC. Even though IBM engineers at the time wanted to use the Motorola 68000 in the PC, the company already had the rights to produce the 8086 line (by trading rights to Intel for its bubble memory) and it could use modified 8085-type components (and 68000-style components were much more scarce).



The development history of Intel family of processors is shown in Table 1. The Very Large Scale Integration (VLSI) technology has been the main driving force behind the development.

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FIR filter

General Purpose Processor

loop:

lw x0, (r0)
lw y0, (r1)
mul a, x0,y0
add b,a,b
inc r0
inc r1
dec ctr
tst ctr
jnz loop
sw b,(r2)
inc r2

This program assumes that the finite window of input signal is stored at the memory location starting from the address specified by r1 and the equal number filter coefficients are stored at the memory location starting from the address specified by r0. The result will be stored at the memory location starting from the address specified by r2. The program assumes the content of the register b as 0 before the start of the loop.

lw x0, (r0)
lw y0, (r1)

These two instructions load x0 and y0 registers with values from the memory location specified by the registers r0 and r1 with values x0 and y0.

mul a, x0,y0
This instruction multiplies x0 with y0 and stores the result in a.

add b,a,b
This instruction adds a with b (which contains already accumulated result from the previous operation) and stores the result in b.

inc r0
inc r1
dec ctr
tst ctr
jnz loop

The above portion of the program increment the registers to point to the next memory location, decrement the counters, to see if the filter order has been reached and tests for 0. It jumps to the start of the loop.

sw b,(r2)
inc r2

This stores the final result and increments the register r2 to point to the next location.

Let us see the program for an early DSP TMS32010 developed by Texas

Instruments in 80s.
It has got the following features
• 16-bit fixed-point
• Harvard architecture separate instruction and data memories
• Accumulator
• Specialized instruction set Load and Accumulate
• 390 ns Multiple-Accumulate(MAC)

TI TMS32010 (Ist DSP) 1982



The program for the FIR filter (for a 3rd order) is given as follows:

Here X4, H4, ... are direct (absolute) memory addresses:
LT X4 ;Load T with x(n-4)
MPY H4 ;P = H4*X4
;Acc = Acc + P
LTD X3 ;Load T with x(n-3); x(n-4) = x(n-3);
MPY H3 ; P = H3*X3
; Acc = Acc + P
LTD X2
MPY H2
...

• Two instructions per tap, but requires unrolling.
; for comment lines.
LT X4 Loading from direct address X4.
MPY H4 Multiply and accumulate.
LTD X3 Loading and shifting in the data points in the memory.

The advantages of the DSP over the General Purpose Processor can be written as Multiplication and Accumulation takes place at a time. Therefore this architecture supports filtering kind of tasks. The loading and subsequent shifting is also takes place at a time.

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Comparison of DSP with General Purpose Processor

Take an Example of FIR filtering both by a General Purpose Processor as well as DSP




An FIR (Finite Impulse Response filter) is represented as shown in the following figure.

The output of the filter is a linear combination of the present and past values of the input. It has several advantages such as:
- Linear Phase.
- Stability.
- Improved Computational Time.




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What is Digital Signal Processing?

Application of mathematical operations to digitally represented signals:
- Signals represented digitally as sequences of samples.
- microphones) and analog-to- digital converters (ADC).
- Digital signals converted back to physical signals via digital-to-analog converters (DAC).
- Digital Signal Processor (DSP): electronic system that processes digital signals.



The above figure represents a Real Time digital signal processing system. The measurand can be temperature, pressure or speech signal which is picked up by a sensor (may be a thermocouple, microphone, a load cell etc). The conditioner is required to filter, demodulate and amplify the signal. The analog processor is generally a low-pass filter used for anti-aliasing effect.

The ADC block converts the analog signals into digital form. The DSP block represents the signal processor. The DAC is for Digital to Analog Converter which converts the digital signals into analog form. The analog low-pass filter eliminates noise introduced by the interpolation in the DAC.



The performance of the signal processing system depends to the large extent on the ADC. The ADC is specified by the number of bits which defines the resolution. The conversion time decides the sampling time. The errors in the ADC are due to the finite number of bits and finite conversion time. Some times the noise may be introduced by the switching circuits.

Similarly the DAC is represented by the number of bits and the settling time at the output.

A DSP tasks requires:
- Repetitive numeric computations.
- Attention to numeric fidelity.
- High memory bandwidth, mostly via array accesses.
- Real-time processing.

And the DSP Design should minimize.
- Cost .
- Power.
- Memory use.
- Development time.

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Evolution of Digital Signal Processors

Introduction

Digital Signal Processing deals with algorithms for handling large chunk of data. This branch identified itself as a separate subject in 70s when engineers thought about processing the signals arising from nature in the discrete form. Development of Sampling Theory followed and the design of Analog-to-Digital converters gave an impetus in this direction. The contemporary applications of digital signal processing was mainly in speech followed by Communication, Seismology, Biomedical etc. Later on the field of Image processing emerged as another important area in signal processing.

The following broadly defines different processor classes

• General Purpose - high performance

- Pentiums, Alpha's, SPARC
- Used for general purpose software
- Heavy weight OS - UNIX, NT
- Workstations, PC's

• Embedded processors and processor cores

- ARM, 486SX, Hitachi SH7000, NEC V800
- Single program
- Lightweight, real-time OS
- DSP support
- Cellular phones, consumer electronics (e. g. CD players)

• Microcontrollers

- Extremely cost sensitive
- Small word size - 8 bit common
- Highest volume processors by far
- Automobiles, toasters, thermostats, ...

A Digital Signal Processor is required to do the following Digital Signal Processing tasks in real time.

• Signal Modeling

- Difference Equation
- Convolution
- Transfer Function
- Frequency Response

• Signal Processing

- Data Manipulation
- Algorithms
- Filtering
- Estimation


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Question and Answere

Q1. Discuss different types of cache mappings.

Ans:
Direct, Fully Associative, Set Associative.

Q2. Discuss the size of the cache memory on the system performance.

Ans:



Q3. Discuss the differences between EDORAM and SDRAM

Ans:
EDO RAM



SDRAM



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DRAM Integration Problem and Memory Management Unit (MMU)

DRAM Integration Problem

• SRAM easily integrated on same chip as processor.

• DRAM more difficult.
o Different chip making process between DRAM and conventional logic.
o Goal of conventional logic (IC) designers:
- minimize parasitic capacitance to reduce signal propagation delays and power consumption.
o Goal of DRAM designers:
- create capacitor cells to retain stored information.
o Integration processes beginning to appear.

Memory Management Unit (MMU)

• Duties of MMU
- Handles DRAM refresh, bus interface and arbitration.
- Takes care of memory sharing among multiple processors.
- Translates logic memory addresses from processor to physical memory addresses of DRAM.

• Modern CPUs often come with MMU built-in.

• Single-purpose processors can be used.

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Variations of DRAMs

Fast Page Mode DRAM (FPM DRAM)

• Each row of memory bit array is viewed as a page.
• Page contains multiple words.
• Individual words addressed by column address.
• Timing diagram:
- row (page) address sent.
- 3 words read consecutively by sending column address for each
extra cycle eliminated on each read/write of words from same.



Extended data out DRAM (EDO DRAM)

• Improvement of FPM DRAM.
• Extra latch before output buffer.
- allows strobing of cas before data read operation completed.
• Reduces read/write latency by additional cycle.



(S)ynchronous and Enhanced Synchronous (ES) DRAM

• SDRAM latches data on active edge of clock.
• Eliminates time to detect ras/cas and rd/wr signals.
• A counter is initialized to column address then incremented on active edge of clock to access consecutive memory locations.
• ESDRAM improves SDRAM
- added buffers enable overlapping of column addressing.
- faster clocking and lower read/write latency possible.



Rambus DRAM (RDRAM)

• More of a bus interface architecture than DRAM architecture.
• Data is latched on both rising and falling edge of clock.
• Broken into 4 banks each with own row decoder.
- can have 4 pages open at a time.
• Capable of very high throughput.


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Advanced RAM

Intoducation

• DRAMs commonly used as main memory in processor based embedded systems.
- high capacity, low cost.

• Many variations of DRAMs proposed.
- need to keep pace with processor speeds.
- FPM DRAM: fast page mode DRAM.
- EDO DRAM: extended data out DRAM.
- SDRAM/ESDRAM: synchronous and enhanced synchronous DRAM.
- RDRAM: rambus DRAM.

Basic DRAM

• Address bus multiplexed between row and column components.
• Row and column addresses are latched in, sequentially, by strobing ras (row address strobe) and cas (column address strobe) signals, respectively.
• Refresh circuitry can be external or internal to DRAM device.
- strobes consecutive memory address periodically causing memory content to be refreshed.
- Refresh circuitry disabled during read or write operation.



Note: In computer or memory technology, a strobe is a signal that is sent that validates data or other signals on adjacent parallel lines. In memory technology, the CAS (column address strobe) and RAS ( row address strobe ) signals are used to tell a dynamic RAM that an address is a column or row address.

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Techniques and Performance of Cache

Cache-Replacement Policy

• Technique for choosing which block to replace.
- when fully associative cache is full.
- when set-associative cache’s line is full.

• Direct mapped cache has no choice.

• Random.
- replace block chosen at random.

• LRU: least-recently used
- replace block not accessed for longest time.

• FIFO: first-in-first-out
- push block onto queue when accessed.
- choose block to replace by popping queue.

Cache Write Techniques

• When written, data cache must update main memory.

• Write-through
- write to main memory whenever cache is written to
easiest to implement.
- processor must wait for slower main memory write
potential for unnecessary writes.

• Write-back
- main memory only written when “dirty” block replaced.
- extra dirty bit for each block set when cache block written to
reduces number of slow main memory writes.

Cache Impact on System Performance

• Most important parameters in terms of performance:

• Total size of cache
- total number of data bytes cache can hold.
- tag, valid and other house keeping bits not included in total

• Degree of associativity.

• Data block size.

• Larger caches achieve lower miss rates but higher access cost.

• Example:
- 2 Kbyte cache: miss rate = 15%, hit cost = 2 cycles, miss cost = 20 cycles
- avg. cost of memory access
= (0.85 * 2) + (0.15 * 20) = 4.7 cycles

• 4 Kbyte cache: miss rate = 6.5%, hit cost = 3 cycles, miss cost will not change.
- avg. cost of memory access = (0.935 * 3) + (0.065 * 20) = 4.105 cycles (improvement).

• 8 Kbyte cache: miss rate = 5.565%, hit cost = 4 cycles, miss cost will not change.
- avg. cost of memory access = (0.94435 * 4) + (0.05565 * 20) = 4.8904 cycles.

Cache Performance Trade-Offs

• Improving cache hit rate without increasing size
- Increase line size
- Change set-associativity



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Basic Techniques of Cache Mapping

Direct Mapping

• Main memory address divided into 2 fields:

•Index which contains
- cache address.
- number of bits determined by cache size.
•Tag
- compared with tag stored in cache at address indicated by index.
- if tags match, check valid bit.

• Valid bit
-indicates whether data in slot has been loaded from memory.

• Offset
-used to find particular word in cache line.



Fully Associative Mapping

• Complete main memory address stored in each cache address.
• All addresses stored in cache simultaneously compared with desired address.
• Valid bit and offset same as direct mapping.



Set-Associative Mapping

• Compromise between direct mapping and fully associative mapping.
• Index same as in direct mapping.
• But, each cache address contains content and tags of 2 or more memory address locations.
• Tags of that set simultaneously compared as in fully associative mapping.
• Cache with set size N called N-way set-associative.
- 2-way, 4-way, 8-way are common.




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Cache Memory

• Usually designed with SRAM.

-faster but more expensive than DRAM.

• Usually on same chip as processor.

- space limited, so much smaller than off-chip main memory.
- faster access (1 cycle vs. several cycles for main memory).

• Cache operation

- Request for main memory access (read or write)
- First, check cache for copy

- cache hit
*copy is in cache, quick access.

-cache miss
*copy not in cache, read address and possibly its neighbors into cache.

• Several cache design choices.
- cache mapping, replacement policies, and write techniques.

Cache Mapping

• is necessary as there are far fewer number of available cache addresses than the memory.

• Are address’ contents in cache?

• Cache mapping used to assign main memory address to cache address and determine hit or miss.

• Three basic techniques:
•Direct mapping.
• Fully associative mapping.
•Set-associative mapping.

• Caches partitioned into indivisible blocks or lines of adjacent memory addresses.
- usually 4 or 8 addresses per line.

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Memory Hierarchy

Objective is to use inexpensive, fast memory

• Main memory
Large, inexpensive, slow memory stores entire program and data.

• Cache
Small, expensive, fast memory stores copy of likely accessed parts of larger memory
Can be multiple levels of cache.




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Questions and Answers

Q1. Discuss the various control signals in a typical RAM device (say HM626)

Ans:



/OE: output enable bar: the output is enables when it is low. It is same as the read bar line
/WE: write enable bar: the line has to made low while writing to this device
CS1: chip select 1 bar: this line has to be made low along with CS2 bar to enable this chip
Q2. Download the datasheet of TC55V2325FF chip and indicate the various signals.

Ans:






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Composing memory

• Memory size needed often differs from size of readily available memories.

• When available memory is larger, simply ignore unneeded high-order address bits and higher data lines

• When available memory is smaller, compose several smaller memories into one larger memory.
– Connect side-by-side to increase width of words.
– Connect top to bottom to increase number of words.

• added high-order address line selects smaller memory containing desired word using a decoder.
– Combine techniques to increase number and width of words.










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Example

HM6264 & 27C256 RAM/ROM devices

• Low-cost low-capacity memory devices.
• Commonly used in 8-bit microcontroller-based embedded systems.
• First two numeric digits indicate device type.
– RAM: 62
– ROM: 27
• Subsequent digits indicate capacity in kilobits.




TC55V2325FF-100 memory device

• 2-megabit synchronous pipelined burst SRAM memory device.
• Designed to be interfaced with 32-bit processors.
• Capable of fast sequential reads and writes as well as single byte I/O.




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Flash Memory and RAM: “Random-access” memory

Flash Memory

It is an extension of EEPROM. It has the same floating gate principle and same write ability and storage permanence. It can be erased at a faster rate i.e. large blocks of memory erased at once, rather than one word at a time. The blocks are typically several thousand bytes large.

• Writes to single words may be slower.
– Entire block must be read, word updated, then entire block written back.
• Used with embedded systems storing large data items in nonvolatile memory.
– e.g., digital cameras, TV set-top boxes, cell phones.

RAM: “Random-access” memory




• Typically volatile memory
– bits are not held without power supply.

• Read and written to easily by embedded system during execution

• Internal structure more complex than ROM
– a word consists of several memory cells, each storing 1 bit
– each input and output data line connects to each cell in its column
– rd/wr connected to every cell
– when row is enabled by decoder, each cell has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read



Basic types of RAM

• SRAM: Static RAM
– Memory cell uses flip-flop to store bit.
– Requires 6 transistors.
– Holds data as long as power supplied.

• DRAM: Dynamic RAM
– Memory cell uses MOS transistor and capacitor to store bit.
– More compact than SRAM.
– “Refresh” required due to capacitor leak.

• word’s cells refreshed when read
– Typical refresh rate 15.625 microsec.
– Slower to access than SRAM.



Ram variations


• PSRAM: Pseudo-static RAM
– DRAM with built-in memory refresh controller.
– Popular low-cost high-density alternative to SRAM.

• NVRAM: Nonvolatile RAM
– Holds data after external power removed.
– Battery-backed RAM.

• SRAM with own permanently connected battery

• writes as fast as reads

• no limit on number of writes unlike nonvolatile ROM-based memory
– SRAM with EEPROM or flash stores complete RAM contents on EEPROM or flash before power.

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Common Memory Types

Read Only Memory (ROM)

This is a nonvolatile memory. It can only be read from but not written to, by a processor in an embedded system. Traditionally written to, “programmed”, before inserting to embedded system.

Uses
– Store software program for general-purpose processor.
• program instructions can be one or more ROM words.
– Store constant data needed by system.
– Implement combinational circuit.



Example

The figure shows the structure of a ROM. Horizontal lines represents the words. The vertical lines give out data. These lines are connected only at circles. If address input is 010 the decoder sets 2nd word line to 1. The data lines Q3 and Q1 are set to 1 because there is a “programmed” connection with word 2’s line. The word 2 is not connected with data lines Q2 and Q0. Thus the output is 1010.



Implementation of Combinatorial Functions

Any combinational circuit of n functions of same k variables can be done with 2k x n ROM. The inputs of the combinatorial circuit are the address of the ROM locations. The output is the word stored at that location.



Mask-programmed ROM

The connections “programmed” at fabrication. They are a set of masks. It can be written only once (in the factory). But it stores data for ever. Thus it has the highest storage permanence. The bits never change unless damaged. These are typically used for final design of high-volume systems.

OTP ROM: One-time programmable ROM

The Connections “programmed” after manufacture by user. The user provides file of desired contents of ROM. The file input to machine called ROM programmer. Each programmable connection is a fuse. The ROM programmer blows fuses where connections should not exist.
• Very low write ability: typically written only once and requires ROM programmer device.
• Very high storage permanence: bits don’t change unless reconnected to programmer and more fuses blown.
• Commonly used in final products: cheaper, harder to inadvertently modify.

EPROM: Erasable programmable ROM

This is known as erasable programmable read only memory. The programmable component is a MOS transistor. This transistor has a “floating” gate surrounded by an insulator. The Negative charges form a channel between source and drain storing a logic 1. The Large positive voltage at gate causes negative charges to move out of channel and get trapped in floating gate storing a logic 0. The (Erase) Shining UV rays on surface of floating-gate causes negative charges to return to channel from floating gate restoring the logic 1. An EPROM package showing quartz window through which UV light can pass.

The EPROM has:
• Better write ability
– can be erased and reprogrammed thousands of times
• Reduced storage permanence
– program lasts about 10 years but is susceptible to radiation and electric noise
• Typically used during design development



EEPROM

EEPROM is otherwise known as Electrically Erasable and Programmable Read Only Memory. It is erased typically by using higher than normal voltage. It can program and erase individual words unlike the EPROMs where exposure to the UV light erases everything.

The EEPROM has:
• Better write ability.
– can be in-system programmable with built-in circuit to provide higher than normal voltage.
• built-in memory controller commonly used to hide details from memory user.
– writes very slow due to erasing and programming.
• “busy” pin indicates to processor EEPROM still writing.
– can be erased and programmed tens of thousands of times.
• Similar storage permanence to EPROM (about 10 years).
• Far more convenient than EPROMs, but more expensive.

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Data Storage

An m word memory can store m x n: m words of n bits each. One word is located at one address therefore to address m words we need.

k = Log2(m) address input signals
or k number address lines can address m = 2k words

Example 4,096 x 8 memory:
• 32,768 bits
• 12 address input signals
• 8 input/output data signals



Memory access

The memory location can be accessed by placing the address on the address lines. The control lines read/write selects read or write. Some memory devices are multi-port i.e. multiple accesses to different locations simultaneously.



Memory Specifications

The specification of a typical memory is as follows:

The storage capacity: The number of bits/bytes or words it can store .

The memory access time (read access and write access): How long the memory takes to load the data on to its data lines after it has been addressed or how fast it can store the data upon supplied through its data lines. This reciprocal of the memory access time is known as Memory.

Bandwidth

The Power Consumption and Voltage Levels: The power consumption is a major factor in embedded systems. The lesser is the power consumption the more is packing density.
Size: Size is directly related to the power consumption and data storage capacity.





There are two important specifications for the Memory as far as Real Time Embedded Systems are concerned.
– Write Ability.
– Storage Performance.

Write ability

It is the manner and speed that a particular memory can be written.
• Ranges of write ability
– High end
• processor writes to memory simply and quickly e.g., RAM
– Middle range
• processor writes to memory, but slower e.g., FLASH, EEPROM (Electrically Erasable and Programmable Read Only Memory)
– Lower range
• special equipment, “programmer”, must be used to write to memory e.g., EPROM, OTP ROM (One Time Programmable Read Only Memory)
– Low end
• bits stored only during fabrication e.g., Mask-programmed ROM
• In-system programmable memory
– Can be written to by a processor in the embedded system using the memory
– Memories in high end and middle range of write ability

Storage permanence

It is the ability to hold the stored bits.

Range of storage permanence.
– High end
• essentially never loses bits.
• e.g., mask-programmed ROM.

– Middle range
• holds bits days, months, or years after memory’s power source turned off.
• e.g., NVRAM

– Lower range
• holds bits as long as power supplied to memory.
• e.g., SRAM

– Low end
• begins to lose bits almost immediately after written.
• e.g., DRAM

Nonvolatile memory
– Holds bits after power is no longer supplied.
– High end and middle range of storage permanence.


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The Memory Interface

Introducation

In a memory read operation the CPU loads the address onto the address bus. Most cases these lines are fed to a decoder which selects the proper memory location. The CPU then sends a read control signal. The data is stored in that location is transferred to the processor via the data lines.

In the memory write operation after the address is loaded the CPU sends the write control signal followed by the data to the requested memory location.

The memory can be classified in various ways i.e. based on the location, power consumption, way of data storage etc



The memory at the basic level can be classified as
1. Processor Memory (Register Array)
2. Internal on-chip Memory
3. Primary Memory
4. Cache Memory
5. Secondary Memory

Processor Memory (Register Array)

Most processors have some registers associated with the arithmetic logic units. They store the operands and the result of an instruction. The data transfer rates are much faster without needing any additional clock cycles. The number of registers varies from processor to processor. The more is the number the faster is the instruction execution. But the complexity of the architecture puts a limit on the amount of the processor memory.

Internal on-chip Memory

In some processors there may be a block of memory location. They are treated as the same way as the external memory. However it is very fast.

Primary Memory

This is the one which sits just out side the CPU. It can also stay in the same chip as of CPU. These memories can be static or dynamic.

Cache Memory

This is situated in between the processor and the primary memory. This serves as a buffer to the immediate instructions or data which the processor anticipates. There can be more than one levels of cache memory.

Secondary Memory

These are generally treated as Input/Output devices. They are much cheaper mass storage and slower devices connected through some input/output interface circuits. They are generally magnetic or optical memories such as Hard Disk and CDROM devices.
The memory can also be divided into Volatile and Non-volatile memory.

* Volatile Memory

The contents are erased when the power is switched off. Semiconductor Random Access Memories fall into this category.

* Non-volatile Memory

The contents are intact even of the power is switched off. Magnetic Memories (Hard Disks), Optical Disks (CDROMs), Read Only Memories (ROM) fall under this category.





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Von-Neumann Architecture

Most of the modern computer system has been designed on the basis of an architecture called Von-Neumann Architecture.



The Memory stores the instructions as well as data. No one can distinguish an instruction and data. The CPU has to be directed to the address of the instruction codes.

The memory is connected to the CPU through the following lines
1. Address
2. Data
3. Control

The von Neumann architecture is a model for a computing machine that uses a single storage structure to hold both the set of instructions on how to perform the computation and the data required or generated by the computation. Such machines are also known as stored-program computers. The separation of storage from the processing unit is implicit in this model.

By treating the instructions in the same way as the data, a stored-program machine can easily change the instructions. In other words the machine is reprogrammable. One important motivation for such a facility was the need for a program to increment or otherwise modify the address portion of instructions. This became less important when index registers and indirect addressing became customary features of machine architecture.


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Questions And Answers

Q1. Enumerate the similarities and differences between the Microcontroller and Digital Signal Processor

Ans:
Microcontrollers usually have on chip RAM and ROM (or EPROM) in addition to on chip i/o hardware to minimize chip count in single chip solutions. As a result of using on chip hardware for I/O and RAM and ROM they usually have pretty low performance CPU. Microcontrollers also often have timers that generate interrupts and can thus be used with the CPU and on chip A/D D/A or parallel ports to get regularly timed I/O. The prime use of a microcontroller is to control the operations of a machine using a fixed program that is stored in ROM and does not change over the lifetime of the system. The microcontroller is concerned with getting data from and to its own pins; the architecture and instruction set are optimized to handle data in bit and byte size.

Digital Signal Processors have been designed based on the modified Harvard Architecture to handle real time signals. The features of these processors are suitable for implementing signal processing algorithms. One of the common operations required in such applications is array multiplication. For example convolution and correlation require array multiplication. This is accomplished by multiplication followed by accumulation and addition. This is generally carried out by Multiplier and Accumulator (MAC) units. Some times it is known as MACD, where D stands for Data move. Generally all the instructions are executed in single cycle. These DSP units generally use Multiple Access and Multi Ported Memory units. Multiple access memory allows more than one access in one clock period. The Multi-ported Memory allows multiple addresses as well Data ports. This also increases the number of access per unit clock cycle.

Q2. Name few chips in each of the family of processors such as: Microcontroller, Digital Signal Processor, General Purpose Processor

Ans:
Microcontroller: Intel 8051, Intel 80196, Motorola 68705
Digital Signal Processors: TI 3206711, TI 3205000
General Purpose Processor: Intel Pentium IV, Power PC


Q3. Enlist the following in the increasing order of their access speed
Flash Memory, Dynamic Memory, Cache Memory, CDROM, Hard Disk, Magnetic Tape, Processor Memory


Ans:
Magnetic Tape, CDROM, Hard Disk, Dynamic Memory, Flash Memory, Cache Memory, Processor Memory

Q4. Draw the circuit of an anti-aliasing Filter using Operational amplifiers


Ans:



Q5. Is it possible to implement an anti-aliasing filter in the digital form?


Ans:
No it is not possible to implement an anti-aliasing filter in digital form. Because aliasing is an error introduced at the sampling phase of analog to digital converter. If the sampling frequency is less than twice of the highest frequency present the higher signal frequencies fold back to lower frequency band and hence can be distinguished in the digital/discrete domain.

Q6. State with justification if the following statements are right (or wrong)
Cache memory can be a static RAM
Dynamic RAMs occupy more space per word storage
The full-form of SDRAM is static-dynamic RAM
BIOS in your PC is not a Random Access Memory (RAM)


Ans:
Cache memory can be a static RAM right
The cache memory need to have very fast access time which is possible with static RAM.

Dynamic RAMs occupy more space per word storage wrong
DRAMs are basically simple MOS based capacitors. Therefore occupy much lower space as compared to static RAMs.

The full-form of SDRAM is static-dynamic RAM wrong
SDRAM is Synchronous Dynamic RAM.

BIOS in your PC is not a Random Access Memory (RAM) Wrong
The BIOS is a CMOS based memory which can be accessed uniformly.


Q7. Explain the function of the following units in a general purpose processor
Instruction Register
Program Counter
Instruction Queue
Control Unit


Ans:
Instruction Register: A register inside the CPU which holds the instruction code temporarily before sending it to the decoding unit.

Program Counter: It is a register inside the CPU which holds the address of the next instruction code in a program. It gets updated automatically by the address generation unit.

Instruction Queue: A set of memory locations inside the CPU to hold the instructions in a pipe-line before rending them to the next instruction decoding unit.

Control Unit: This is responsible in generating timing and control signals for various operations inside the CPU. It is very closely associated with the instruction decoding unit.

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Memory And Input/Output Devices

Memory

Memory serves processor short and long-term information storage requirements while registers serve the processor’s short-term storage requirements. Both the program and the data are stored in the memory. This is known as Princeton Architecture where the data and program occupy the same memory. In Harvard Architecture the program and the data occupy separate memory blocks. The former leads to simpler architecture. The later needs two separate connections and hence the data and program can be made parallel leading to parallel processing. The general purpose processors have the Princeton Architecture.

The memory may be Read-Only-Memory or Random Access Memory (RAM). It may exist on the same chip with the processor itself or may exist outside the chip. The on-chip memory is faster than the off-chip memory. To reduce the access (read-write) time a local copy of a portion of memory can be kept in a small but fast memory called the cache memory. The memory also can be categorized as Dynamic or Static. Dynamic memory dissipate less power and hence can be compact and cheaper. But the access time of these memories are slower than their Static counter parts. In Dynamic RAMs (or DRAM) the data is retained by periodic refreshing operation. While in the Static Memory (SRAM) the data is retained continuously. SRAMs are much faster than DRAMs but consume more power. The intermediate cache memory is an SRAM.

In a typical processor when the CPU needs data, it first looks in its own data registers. If the data isn't there, the CPU looks to see if it's in the nearby Level 1 cache. If that fails, it's off to the Level 2 cache. If it's nowhere in cache, the CPU looks in main memory. Not there? The CPU gets it from disk. All the while, the clock is ticking, and the CPU is sitting there waiting.


Input/Output Devices and Interface Chips

Typical RTES interact with the environment and users through some inbuilt hardware. Occasionally external circuits are required for communicating with user, other computers or a network.

In the mobile handset discussed earlier the input output devices are, keyboard, the display screen, the antenna, the microphone, speaker, LED indicators etc. The signal to these units may be analog or digital in nature. To generate an analog signal from the microprocessor we need an Digital to Analog Converter(DAC) and to accept analog signal we need and Analog to Digital Converter (ADC). These DAC and ADC again have certain control modes. They may also operate at different speed than the microprocessor. To synchronize and control these interface chips we may need another interface chip. Similarly we may have interface chips for keyboard, screen and antenna. These chips serve as relaying units to transfer data between the processor and input/output devices. The input/output devices are generally slower than the processor. Therefore, the processor may have to wait till they respond to any request for data transfer. Number of idle clock cycles may be wasted for doing so. However, the input-output interface chips carry out this task without making the processor to wait or idle.



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A Basic Microprocessors vs A Basic DSP

General Purpose Processor



Characterization of General Purpose Processor

1. CPUs for PCs and workstations E.g., Intel Pentium IV
2. Von Neumann architecture
3. Typically 1 access per cycle
4. Most operations take more than 1 cycle
5. General-purpose instructions Typically only one operation per instruction
6. Often, no separate address generation units
7. General-purpose addressing modes
8. Software loops only
9. Interrupts rarely disabled
10. Register shadowing common
11. Dynamic caches are common
12. Wide range of on-chip and off-chip peripherals and I/O interfaces
13. Asynchronous serial port...

A Basic DSP



DSP Characterization

1. Microprocessors specialized for signal processing applications.
2. Harvard architecture
3. Two to Four memory accesses per cycle
4. Dedicated hardware performs all key arithmetic operations in 1 cycle
5. Very limited SIMD(Single Instruction Multiple Data) features and Specialized, complex instructions
6. Multiple operations per instruction
7. Dedicated address generation units
8. Specialized addressing [• Auto-increment • Modulo (circular) Bit-reversed ]
9. Hardware looping.
10. Interrupts disabled during certain operations
11. Limited or no register Shadowing
12. Rarely have dynamic features
13. Relatively narrow range of DSP oriented on-chip peripherals and I/O interfaces
14. synchronous serial port



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Microprocessors vs Microcontrollers

Microprocessors

A microprocessor is a general-purpose digital computer’s central processing unit. To make a complete microcomputer, you add memory (ROM and RAM) memory decoders, an oscillator, and a number of I/O devices. The prime use of a microprocessor is to read data, perform extensive calculations on that data, and store the results in a mass storage device or display the results. These processors have complex architectures with multiple stages of pipelining and parallel processing. The memory is divided into stages such as multi-level cache and RAM. The development time of General Purpose Microprocessors is high because of a very complex VLSI design.




Microcontrollers

The design of the microcontroller is driven by the desire to make it as expandable and flexible as possible. Microcontrollers usually have on chip RAM and ROM (or EPROM) in addition to on chip i/o hardware to minimize chip count in single chip solutions. As a result of using on chip hardware for I/O and RAM and ROM they usually have pretty low performance CPU. Microcontrollers also often have timers that generate interrupts and can thus be used with the CPU and on chip A/D D/A or parallel ports to get regularly timed I/O. The prime use of a microcontroller is to control the operations of a machine using a fixed program that is stored in ROM and does not change over the lifetime of the system. The microcontroller is concerned with getting data from and to its own pins; the architecture and instruction set are optimized to handle data in bit and byte size.




The contrast between a microcontroller and a microprocessor is best exemplified by the fact that most microprocessors have many operation codes (opcodes) for moving data from external memory to the CPU; microcontrollers may have one or two. Microprocessors may have one or two types of bit-handling instructions; microcontrollers will have many.


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